Simulation packets for SiTCP

SiTCPライブラリ入門者用 / SiTCP library beginners SiTCPに関する質問など / Questions
1

Hi,
we plan on using either the SiTCP or SiTCPXG in our project, however we still don’t have the necessary hardware. We are targeting an Kintex Ultrascale device. Till our hardware arrive is there any test data that could be used to do an RTL level simulation? The main reason is because since there are design example for various boards I would like to compare my KCU implementation against the example designs.

Thanks
—Ioannis

2

Thank you for posting.
Unfortunately, there is no test bench.
However, since SiTCP is published on the netlist, simulation from the top is possible.
It can be simulated by inputting TCP / IP packets from GMII.
The release schedule for SiTCP-XG for Kintex Ultrascale devices has not yet been decided.

Best regards

3

I’m glad you used this site right away.
I hope this site will answer your question.
Please consider adopting SiTCP.

4

Hi,
I have setup my top-level simulation, however the core doesn’t seem to behave as expected. I am reseting to begin with and then lower the RST port. Looking at the SiTCP_RST signal I should expect it to change, however what I see is that it stays to high impedance (‘Z’) I am trying to use the default values for the IP, TCP port and RBCP port. is there anything else I need to do?
Thanks
–Ioannis

5

Hi,

I think this is the reason why it doesnt seem to come up, is there a specific way to set it in client mode?

Thanks
Ioannis

6

Thank you for posting.
Synthesis is required to simulate the SiTCP netlist. Then select Run Post-Synthesis Functional Simulation. It takes time to release the reset, so apply a pulse to TIM_1S about twice.
However, when simulating RBCP (UDP), it is necessary to input Ethernet frames, so unless there is a specific reason, SiTCP simulation is not recommended. At the time of simulation, it is better to use the SiTCP model instead of the core to check the user circuit. Please refer to “SiTCP Manual” to create the SiTCP model. Since the signal connected to the PHY is not subject to simulation, there is no problem if it is not connected.

I hope you will find the information useful.