****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
Sourcing tcl script ‘~/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl’
source vc707sitcp.tcl -notrace
create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1412.906 ; gain = 0.000
Command: synth_design -top vc707sitcp -part xc7vx485tffg1761-2
Starting synth_design
Attempting to get a license for feature ‘Synthesis’ and/or device ‘xc7vx485t’
INFO: [Common 17-349] Got license for feature ‘Synthesis’ and/or device ‘xc7vx485t’
INFO: [Device 21-403] Loading part xc7vx485tffg1761-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 22480
...(中略)...
Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1831.617 ; gain = 418.836
Synthesis finished with 0 errors, 0 critical warnings and 3 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:20 . Memory (MB): peak = 1831.617 ; gain = 284.117
Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1831.617 ; gain = 418.836
INFO: [Project 1-571] Translating synthesized netlist
Parsing EDIF File [~/SiTCP_Sample_Code_for_VC707_SGMII/WRAP_gig_ethernet_pcs_pma_0.edf]
Finished Parsing EDIF File [~/SiTCP_Sample_Code_for_VC707_SGMII/WRAP_gig_ethernet_pcs_pma_0.edf]
Release 14.7 - ngc2edif P_INT.20191124 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design fifo_generator_v11_0.ngc …
WARNING:NetListWriters:298 - No output is written to fifo_generator_v11_0.xncf,
ignored.
…