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Recent SiTCP core and FPGA families
投稿日時 2017/4/6 21:56
I noticed that the SiTCP netlists for recent FPGA families like Virtex-7 are available in new versions. The changelog for version 10.0, in particular, says "RX bug fixed". I was wondering whether the mentioned bug also affects older FPGA families like Virtex-4 and Virtex-5, and whether the new netlists will be made available for these as well.
投稿日時 2017/4/7 9:21
Recent modifications are addition of functions and correction of minor bugs.
Therefore, FPGA for new design is released in order.
It takes time to respond to all families.
Families requested by the forum are striving to be released preferentially.
投稿日時 2017/4/11 16:55
OK, thank you for the information. Does that mean that the bug mentioned in the V10 changelog is not relevant for Virtex-4 and Virtex-5?
投稿日時 2017/4/11 17:20
Functions and bug of libraries of the same version do not depend on the family of FPGAs.
The bugs fixed in V10 are also Virtex-4 and Virtex-5.
投稿日時 2017/4/11 18:03
I see. Since I don't know what exactly the bug is, I was wondering if it might bite us at some point in the future. Can the fixed netlists also be made available for the Virtex-4 (FX60) and Virtex-5 (FX70T)?
投稿日時 2017/4/11 18:09
A bug occurs when using a 64 kbyte receive buffer.
SiTCP-V10 for Virtex-4 and Virtex-5 will be released as soon as possible.
投稿日時 2017/4/11 19:01
OK, perfect. Thank you very much!
投稿日時 2017/4/21 13:40
Now, SiTCP-V10 for Virtex-5 has just been released.
SiTCP-V10 for Virtex-4 will be released later.
投稿日時 2017/5/4 0:05
Hi. Is there any update on when the Virtex-4 version may be released? We'd like to include the updated netlists in our next firmware release, and we want to avoid changing the Virtex-4 and Virtex-5 versions separately. Thank you!
投稿日時 2017/5/8 14:49
SiTCP-V10 for Virtex-4 has just been released.
Sorry to have kept you waiting.
投稿日時 2017/5/8 23:33
Thank you very much for providing the netlist. We have incorporated it into our newest firmware release.